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t5761 T5760 / preliminary information rev. a2, 19-oct-00 1 (32) uhf ask/fsk receiver description the T5760/t5761 is a multi-chip pll receiver device supplied in an so20 package. it has been especially de- veloped for the demands of rf low-cost data transmission systems with data rates from 1 kbaud to 10 kbaud in manchester or bi-phase code. the receiver is well suited to operate with the atmel wireless & microcontrollers? pll rf transmitter t5750. its main applications are in the areas of telemetering, security technology and key- less-entry systems. it can be used in the frequency receiving range of f 0 = 868 to 870 mhz or f 0 = 902 to 928 mhz for ask or fsk data transmission. all the statements made below refer to 868.3 mhz and 915.0 mhz applications. features fully integrated lc-vco and pll loop filter very high sensitivity with power matched lna 30 db image rejection high system iip3 (?16 dbm), system 1-db compres- sion point (?25 dbm) high large-signal capability at gsm band (blocking ?30 dbm @ + 20 mhz, iip3 = ?12 dbm @ + 20 mhz) 5 v to 20 v automotive compatible data interface data clock available for manchester- and bi-phase- coded signals programmable digital noise suppresion receiving bandwidth b if = 600 khz for low cost 90-ppm crystals low power consumption due to configurable polling temperature range ?40 c to 105 c esd protection 2 kv hbm, 200 v mm communication to c possible via a single bi-directional data line low-cost solution due to high integration level with minimum external circuitry requirements system block diagram demod. if amp lna vco pll xto control T5760/ t5761 1...5 c power amp. xto vco pll t5750 antenna antenna uhf ask/fsk remote control transmitter uhf ask/fsk remote control receiver figure 1. system block diagram ordering information extended type number package remarks T5760-tg so20 tube, for 868 mhz ism band T5760-tgq so20 taped and reeled, for 868 mhz ism band t5761-tg so20 tube, for 915 mhz ism band t5761-tgq so20 taped and reeled, for 915 mhz ism band
T5760 t5761 / rev. a2, 19-oct-00 preliminary information 2 (32) pin description pin symbol function 1 sens sensitivity-control resistor 2 ic_ active ic condition indicator low = sleep mode high = active mode 3 cdem lower cut-off frequency data fil- ter 4 avcc analog power supply 5 test 1 test pin, during operation at gnd 6 agnd analog ground 7 n.c. not connected, connect to gnd 8 lnaref high-frequency reference node lna and mixer 9 lna_in rf input 10 lnagnd dc ground lna and mixer 11 test 2 do not connect during operating 12 test 3 test pin, during operation at gnd 13 n.c. not connected, connect to gnd 14 xtal crystal oscillator xtal connec- tion 15 dvcc digital power supply 16 test 4 test pin, during operation at dvcc 17 data_ clk bit clock of data stream 18 dgnd digital ground 19 poll- ing/_on selects polling or rceiving mode low: receiving mode high: polling mode 20 data data output / configuration input 1 2 3 4 5 6 7 8 10 9 19 18 17 16 14 15 13 12 11 20 avcc test 1 agnd n.c. lnaref lna_in ic_active cdem data_clk test 4 xtal n.c. test 3 polling /_on dgnd lnagnd test 2 data dvcc sens T5760/ t5761 figure 2. pinning so20
t5761 T5760 / preliminary information rev. a2, 19-oct-00 3 (32) block diagram sens cdem avcc agnd dgnd lnagnd lna_in data polling/_on data_clk dvcc xtal polling circuit and control logic rssi limiter out lc ? vco f :256 xto standby logic fe clk fsk/ask ? demodulator and data filter rssi if amp. poly ? lpf fg=7mhz lna 4. order f0=950 khz/ dem_out sensitivity ? reduction lpf fg=2.2mhz if amp. ic_active data ? interface lnaref f :2 loop ? filter 1 mhz figure 3. block diagram rf front end the rf front end of the receiver is a low-if heterodyne configuration that converts the input signal into a 950-khz/ 1-mhz if signal with an image rejection of typ- ical 30db. according to figure 3 the front end consists of an lna (low noise amplifier), lo (local oscillator), i/q mixer, polyphase lowpass filter and an if amplifier. the pll generates the carrier frequency for the mixer via a full integrated synthesizer with integrated low noise lc-vco (voltage controlled oscillator ) and pll-loop- filter. the xto ( crystal oscillator ) generates the reference frequency f xto . the integrated lc-vco gen- erates two times the mixer drive frequency f vco . the i/q signals for the mixer are generated with a divide by two circuit ( f lo = f vco /2 ). f vco is divided by a factor of 256 and feed into a phase frequency detector and compared with f xto . the output of the phase frequency detector is feed into an integrated loopfilter and thereby generates the control voltage for the vco. if f lo is determined, f xto can be calculated using the following formula: f xto = f lo / 128 the xto is a one-pin oscillator that operates at the series resonance of the quartz crystal with high current but low voltage signal, so that there is only a small voltage at the crystal oscillator frequency at pin xtal. according to figure 4, the crystal should be connected to gnd with a series capacitor c l . the value of that capacitor is recom- mended by the crystal supplier. due to a somewhat inductive impedance at steady state oscillation and some pcb parasitics a lower value of c l is normally necessary.
T5760 t5761 / rev. a2, 19-oct-00 preliminary information 4 (32) the value of c l should be optimized for the individual board layout to achieve the exact value of f xto (the best way is to use a crystal with known load resonance fre- quency to find the right value for this capacitor) and hereby of f lo . when designing the system in terms of re- ceiving bandwidth and local oscillator accuracy, the accuracy of the crystal and the xto must be considered. if a crystal with 30 ppm adjustment tolerance at 25 c , 50ppm over temperature ? 40 c to 105 c, 10 ppm of total aging and a cm ( motional capacitance ) of 7 ff is used, an additional xto pulling of 30 ppm has to be added. the resulting total lo tolerance of 120ppm agrees with the receiving bandwidth specification of the T5760/t5761 if the t5750 has also a total lo tolerance of 120 ppm. dvcc xtal test 3 test 2 n.c. v c s l figure 4. xto peripherals the nominal frequency f lo is determined by the rf input frequency f rf and the if frequency f if using the following formula (low side injection): f lo = f rf ? f if to determine f lo , the construction of the if filter must be considered at this point. the nominal if frequency is f if = 950 khz. to achieve a good accuracy of the filter corner frequencies, the filter is tuned by the crystal fre- quency f xto . this means that there is a fixed relation between f if and f lo . f if = f lo / 915 the relation is designed to achieve the nominal if fre- quency of f if = 950 khz for the 868.3 mhz version. for the 915 mhz version an if frequency of f if = 1.0 mhz results. the rf input either from an antenna or from a rf genera- tor must be transformed to the rf input pin lna_in. the input impedance of that pin is provided in the electrical parameters. the parasitic board inductances and capaci- tances influence the input matching. the rf receiver T5760/t5761 exhibits its highest sensitivity if the lna is power matched. this makes the matching to an saw filter as well as to 50 or an antenna more easy. figure 33 shows a typical input matching network for f rf = 868.3 mhz to 50 . figure 34 illustrates an according input matching for 868.3 mhz to an saw. the input matching network shown in figure 33 is the reference net- work for the parameters given in the electrical characteristics. analog signal processing if filter the signals coming from the rf front end are filtered by the fully integrated 4th-order if filter. the if center fre- quency is f if = 950 khz for applications where f rf = 868.3 mhz and f if =1.0 mhz for f rf = 915 mhz. the nominal bandwidth is 600 khz. limiting rssi amplifier the subsequent rssi amplifier enhances the output signal of the if amplifier before it is fed into the demod- ulator. the dynamic range of this amplifier is dr rssi = 60 db. if the rssi amplifier is operated within its linear range, the best s/n ratio is maintained in ask mode. if the dyn amic range is exceeded by the transmitter signal, the s/n ratio is defined by the ratio of the maxi- mum rssi output voltage and the rssi output voltage due to a disturber. the dynamic range of the rssi ampli- fier is exceeded if the rf input signal is about 60 db higher compared to the rf input signal at full sensitivity. in fsk mode the s/n ratio is not affected by the dynamic range of the rssi amplifier, because only the hard limited signal from a high gain limiting amplifier is used by the demodulator. the output voltage of the rssi amplifier is internally compared to a threshold voltage v th_red . v th_red is deter- mined by the value of the external resistor r sens . r sens is connected between pin sens and gnd or v s . the output of the comparator is fed into the digital control logic. by this means it is possible to operate the receiver at a lower sensitivity. if r sens is connected to gnd, the receiver switches to full sensitivity. it is also possible to connect the pin sens di- rectly to gnd to get the maximum sensitivity. if r sens is connected to v s , the receiver operates at a lower sensitivity. the reduced sensitivity is defined by the value of r sens , the maximum sensitivity by the signal-to- noise ratio of the lna input. the reduced sensitivity depends on the signal strength at the output of the rssi amplifier. since different rf input networks may exhibit slightly different values for the lna gain, the sensitivity values given in the electrical characteristics refer to a specific input matching. this matching is illustrated in figure 33
t5761 T5760 / preliminary information rev. a2, 19-oct-00 5 (32) and exhibits the best possible sensitivity and at the same time power matching at rf_in. r sens can be connected to v s or gnd via a c. the receiver can be switched from full sensitivity to reduced sensitivity or vice versa at any time. in polling mode, the receiver will not wake up if the rf input signal does not exceed the selected sensitivity. if the receiver is already active, the data stream at pin data will disappear when the input signal is lower than defined by the reduced sensitivity. instead of the data stream, the pattern accord- ing to figure 5 is issued at pin data to indicate that the receiver is still active (see also figure 32). data t data_l_max data_min t figure 5. steady l state limited data output pattern fsk/ask demodulator and data filter the signal coming from the rssi amplifier is converted into the raw data signal by the ask/fsk demodulator. the operating mode of the demodulator is set via the bit ask/_fsk in the opmode register. logic ? l ? sets the demodulator to fsk, applying ? h ? to ask mode. in ask mode an automatic threshold control circuit (atc) is employed to set the detection reference voltage to a value where a good signal to noise ratio is achieved. this circuit also implies the effective suppression of any kind of in-band noise signals or competing transmitters. if the s/n (ratio to suppress in-band noise signals) ex- ceeds about 10 db the data signal can be detected properly, but better values are found for many modulation schemes of the competing transmitter. the fsk demodulator is intended to be used for an fsk deviation of 10 khz f 100 khz. in fsk mode the data signal can be detected if the s/n (ratio to suppress inband noise signals) exceeds about 2 db. this value is valid for all modulation schemes of a disturber signal. the output signal of the demodulator is filtered by the data filter before it is fed into the digital signal processing circuit. the data filter improves the s/n ratio as its pass- band can be adopted to the characteristics of the data signal. the data filter consists of a 1 st -order highpass and a 2 nd -order lowpass filter the highpass filter cut-off frequency is defined by an external capacitor connected to pin cdem. the cut-off frequency of the highpass filter is defined by the follow- ing formula: fcu_df 1 2 30 k cdem in self-polling mode, the data filter must settle very rapidly to achieve a low current consumption. therefore, cdem cannot be increased to very high values if self- polling is used. on the other hand cdem must be large enough to meet the data filter requirements according to the data signal. recommended values for cdem are given in the electrical characteristics. the cut-off frequency of the lowpass filter is defined by the selected baud-rate range (br_range). the br_range is defined in the opmode register (refer to chapter ? configuration of the receiver ? ). the br_range must be set in accordance to the used baud-rate. the T5760/t5761 is designed to operate with data coding where the dc level of the data signal is 50%. this is valid for manchester and bi-phase coding. if other modulation schemes are used, the dc level should always remain within the range of v dc_min = 33% and v dc_max = 66%. the sensitivity may be reduced by up to 2 db in that condition. each br_range is also defined by a minimum and a maximum edge-to-edge time (t ee_sig ). these limits are defined in the electrical characteristics. they should not be exceeded to maintain full sensitivity of the receiver. receiving characteristics the rf receiver T5760/t5761 can be operated with and without a saw front-end filter. in a typical automotive application, a saw filter is used to achieve better selec- tivity and large signal capability. the receiving frequency response without a saw front-end filter is illustrated in figures 6 and 7. this example relates to ask mode. fsk mode exhibit similar behavior. the plots are printed rela- tively to the maximum sensitivity. if a saw filter is used, an insertion loss of about 3 db must be considered, but the over all selectivity is much better. when designing the system in terms of receiving band- width, the lo deviation must be considered as it also determines the if center frequency. the total lo devi- ation is calculated to be the sum of the deviation of the crystal and the xto deviation of the T5760/t5761. low- cost crystals are specified to be within 90 ppm over tolerance, temperature and aging. the xto deviation of the T5760/t5761 is an additional deviation due to the xto circuit. this deviation is specified to be 30 ppm worst case for a crystal with cm = 7 ff. if a crystal of 90 ppm is used, the total deviation is 120 ppm in that case. note that the receiving bandwidth and the if-filter bandwidth are equivalent in ask mode but not in fsk mode.
T5760 t5761 / rev. a2, 19-oct-00 preliminary information 6 (32) ? 60 ? 50 ? 40 ? 30 ? 20 ? 10 0 ? 4 ? 3 ? 2 ? 101234 df ( mhz ) dp ( db ) figure 6. narrow band receiving frequency response ? 100 ? 80 ? 60 ? 40 ? 20 0 ? 12 ? 9 ? 6 ? 3036912 df ( mhz ) dp ( db ) figure 7. wide band receiving frequency response polling circuit and control logic the receiver is designed to consume less than 1 ma while being sensitive to signals from a corresponding trans- mitter. this is achieved via the polling circuit. this circuit enables the signal path periodically for a short time. during this time the bit-check logic verifies the presence of a valid transmitter signal. only if a valid signal is detected the receiver remains active and transfers the data to the connected c. if there is no valid signal present the receiver is in sleep mode most of the time resulting in low current consumption. this condition is called polling mode. a connected c is disabled during that time. all relevant parameters of the polling logic can be config- ured by the connected c. this flexibility enables the user to meet the specifications in terms of current con- sumption, system response time, data rate etc. regarding the number of connection wires to the c, the receiver is very flexible. it can be either operated by a single bi-directional line to save ports to the connected c or it can be operated by up to five uni-directional ports. basic clock cycle of the digital circuitry the complete timing of the digital circuitry and the analog filtering is derived from one clock. this clock cycle t clk is derived from the crystal oscillator (xto) in combination with a divide by 14 circuit. according to chapter ? rf front end ? , the frequency of the crystal oscil- lator (f xto ) is defined by the rf input signal (f rfin ) which also defines the operating frequency of the local oscillator (f lo ). the basic clock cycle is t clk = 14/ f xto giving t clk = 2.066 s for f rf = 868.3 mhz and t clk = 1.961 s for f rf = 915 mhz t clk controls the following application-relevant parame- ters: timing of the polling circuit including bit check timing of the analog and digital signal processing timing of the register programming frequency of the reset marker if filter center frequency (f if0 ) most applications are dominated by two transmission fre- quencies: f transmit = 915 mhz is mainly used in usa, f transmit = 868.3 mhz in europe. in order to ease the usage of all t clk -dependent parameters on this electrical characteristics display three conditions for each parame- ter. application usa (f xto = 7.14063 mhz, t clk = 1.961 s) application europe (f xto = 6.77617 mhz, t clk = 2.066 s) other applications the electrical characteristic is given as a function of t clk . the clock cycle of some function blocks depends on the selected baud-rate range (br_range) which is defined in the opmode register. this clock cycle t xclk is defined by the following formulas for further reference: br_range = br_range0: t xclk = 8 t clk br_range1: t xclk = 4 t clk br_range2: t xclk = 2 t clk br_range3: t xclk = 1 t clk polling mode according to figure 11, the receiver stays in polling mode in a continuous cycle of three different modes. in sleep mode the signal processing circuitry is disabled for the time period t sleep while consuming low current of i s = i soff . during the start-up period, t startup , all signal processing circuits are enabled and settled. in the follow-
t5761 T5760 / preliminary information rev. a2, 19-oct-00 7 (32) ing bit-check mode, the incoming data stream is analyzed bit by bit contra a valid transmitter signal. if no valid signal is present, the receiver is set back to sleep mode af- ter the period t bit-check . this period varies check by check as it is a statistical process. an average value for t bit-check is given in the electrical characteristics. during t startup and t bit-check the current consumption is i s = i son . the condition of the receiver is indicated on pin ic_ac- tive. the average current consumption in polling mode is dependent on the duty cycle of the active mode and can be calculated as: i spoll i soff t sleep i son (t startup t bitcheck ) t sleep t startup t bitcheck during t sleep and t startup the receiver is not sensitive to a transmitter signal. to guarantee the reception of a trans- mitted command the transmitter must start the telegram with an adequate preburst. the required length of the preburst depends on the polling parameters t sleep , t startup , t bit-check and the start-up time of a connected c (t start, c ). thus, t bit-check depends on the actual bit rate and the number of bits (n bit-check ) to be tested. the following formula indicates how to calculate the preburst length. t preburst t sleep + t startup + t bit-check + t start_ c sleep mode the length of period t sleep is defined by the 5-bit word sleep of the opmode register, the extension factor xsleep (according to table 9), and the basic clock cycle t clk . it is calculated to be: t sleep = sleep x sleep 1024 t clk in us- and european applications, the maximum value of t sleep is about 60 ms if xsleep is set to 1. the time reso- lution is about 2 ms in that case. the sleep time can be extended to almost half a second by setting xsleep to 8. xsleep can be set to 8 by bit xsleep std to ? 1 ? . according to table 8, the highest register value of sleep sets the receiver into a permanent sleep condition. the re- ceiver remains in that condition until another value for sleep is programmed into the opmode register. this function is desirable where several devices share a single data line and may also be used for c polling ? via pin polling/_on, the receiver can be switched on and off.
T5760 t5761 / rev. a2, 19-oct-00 preliminary information 8 (32) sleep mode: all circuits for signal processing are disabled. only xto and polling logic is enabled. output level on pin ic_active => low i s = i soff t sleep = sleep x sleep 1024 t clk start-up mode: the signal processing circuits are enabled. after the start-up time (t startup ) all circuits are in stable condition and ready to receive. output level on pin ic_active => high i s = i son t startup bit-check mode: the incomming data stream is analyzed. if the timing indicates a valid transmitter signal, the receiver is set to receiving mode. otherwise it is set to sleep mode. output level on pin ic_active => high i s = i son t bit-check receiving mode: the receiver is turned on permanently and passes the data stream to the connected c. it can be set to sleep mode through an off command via pin data or polling/_on. output level on pin ic_active => high i s = i son bit check ok ? off command sleep: 5-bit word defined by sleep0 to sleep4 in opmode register x sleep : extension factor defined by xsleep std according to table 9 t clk : basic clock cycle defined by f xto and pin mode t startup : is defined by the selected baud rate range and t clk . the baud-rate range is defined by baud0 and baud1 in the opmode register. t bit-check: depends on the result of the bit check if the bit check is ok, t bit-check depends on the number of bits to be checked (n bit-check ) and on the utilized data rate. if the bit check fails, the average time period for that check depends on the selected baud-rate range and on t clk . the baud-rate range is defined by baud0 and baud1 in the opmode register. no yes figure 8. polling mode flow chart bit check ic_active data_out (data) 1/2 bit start ? up mode ( number of checked bits: 3 ) bit check ok 1/2 bit 1/2 bit 1/2 bit 1/2 bit 1/2 bit receiving mode dem_out bit ? check mode t start ? up t bit ? check figure 9. timing diagram for complete successful bit check
t5761 T5760 / preliminary information rev. a2, 19-oct-00 9 (32) bit-check mode in bit-check mode the incoming data stream is examined to distinguish between a valid signal from a correspond- ing transmitter and signals due to noise. this is done by subsequent time frame checks where the distances be- tween 2 signal edges are continuously compared to a programmable time window. the maximum count of this edge-to-edge tests before the receiver switches to receiv- ing mode is also programmable. configuring the bit check assuming a modulation scheme that contains 2 edges per bit, two time frame checks are verifying one bit. this is valid for manchester, bi-phase and most other modula- tion schemes. the maximum count of bits to be checked can be set to 0, 3, 6 or 9 bits via the variable n bit-check in the opmode register. this implies 0, 6, 12 and 18 edge to edge checks respectively. if n bit-check is set to a higher value, the receiver is less likely to switch to receiving mode due to noise. in the presence of a valid transmitter signal, the bit check takes less time if n bit-check is set to a lower value. in polling mode, the bit-check time is not dependent on n bit-check . figure 12 shows an example where 3 bits are tested successfully and the data signal is transferred to pin data. according to figure 13, the time window for the bit check is defined by two separate time limits. if the edge-to-edge time t ee is in between the lower bit-check limit t lim_min and the upper bit-check limit t lim_max , the check will be continued. if t ee is smaller than t lim_min or t ee exceeds t lim_max , the bit check will be terminated and the re- ceiver switches to sleep mode. dem_out t ee t lim_min t lim_max 1/f sig figure 10. valid time window for bit check for best noise immunity it is recommended to use a low span between t lim_min and t lim_max . this is achieved us- ing a fixed frequency at a 50% duty cycle for the transmitter preburst. a ? 11111... ? or a ? 10101... ? sequence in manchester or bi-phase is a good choice concerning that advice. a good compromise between receiver sensi- tivity and susceptibility to noise is a time window of 25% regarding the expected edge-to-edge time t ee . us- ing pre-burst patterns that contain various edge-to-edge time periods, the bit-check limits must be programmed according to the required span. the bit-check limits are determined by means of the for- mula below. t lim_min = lim_min t xclk t lim_max = (lim_max ? 1) t xclk lim_min and lim_max are defined by a 5-bit word each within the limit register. using above formulas, lim_min and lim_max can be de- termined according to the required t lim_min , t lim_max and t xclk . the time resolution defining t lim_min and t lim_max is t xclk . the minimum edge-to-edge time t ee (t data_l_min , t data_h_min ) is defined according to the chapter ? receiving mode ? . the lower limit should be set to lim_min 10. the maximum value of the upper limit is lim_max = 63. if the calculated value for lim_min is < 19, it is recom- mended to check 6 or 9 bits (n bit-check ) to prevent switching to receiving mode due to noise. figures 14, 15 and 16 illustrate the bit check for the bit- check limits lim_min = 14 and lim_max = 24. when the ic is enabled, the signal processing circuits are en- abled during t startup . the output of the ask/ fsk demodulator (dem_out) is undefined during that period. when the bit check becomes active, the bit-check counter is clocked with the cycle t xclk . figure 14 shows how the bit check proceeds if the bit- check counter value cv_lim is within the limits defined by lim_min and lim_max at the occurrence of a signal edge. in figure 15 the bit check fails as the value cv_lim is lower than the limit lim_min. the bit check also fails if cv_lim reaches lim_max. this is illustrated in figure 16.
T5760 t5761 / rev. a2, 19-oct-00 preliminary information 10 (32) bit check ic_active dem_out bit ? check ? counter 0 2 345 6 245 1 7 81 36789111213 14 10 1/2 bit 15 16 17 18 1 234 56 ( lim_min = 14, lim_max = 24 ) 7891011 12 13 14 15 1234 1/2 bit 1/2 bit bit check ok bit check ok t xclk start ? up mode bit ? check mode t start ? up t bit ? check figure 11. timing diagram during bit check bit check ic_active bit?check? counter 0 2345 6 245 1 1 3 6789 1112 10 1/2 bit start ? up mode 0 ( lim_min = 14, lim_max = 24 ) sleep mode bit check failed ( cv_lim < lim_min ) dem_out bit ? check mode t start ? up t bit ? check t sleep figure 12. timing diagram for failed bit check (condition: cv_lim < lim_min) bit check ic_active bit ? check ? counter 0 2345 6 245 1 7 367 8 9 11 12 10 1/2 bit start ? up mode 20 ( lim_min = 14, lim_max = 24 ) sleep mode bit check failed ( cv_lim >= lim_max ) 13 14 15 16 17 18 19 21 22 23 24 0 1 dem_out bit ? check mode t start ? up t bit ? check t sleep figure 13. timing diagram for failed bit check (condition: cv_lim > = lim_max) duration of the bit check if no transmitter signal is present during the bit check, the output of the ask/ fsk demodulator delivers random signals. the bit check is a statistical process and t bit-check varies for each check. therefore, an average value for t bit-check is given in the electrical characteristics. t bit-check depends on the selected baud-rate range and on t clk . a higher baud-rate range causes a lower value for t bit-check resulting in a lower current consumption in pol- ling mode. in the presence of a valid transmitter signal, t bit-check is dependent on the frequency of that signal, f sig , and the count of the checked bits, n bit-check . a higher value for n bit-check thereby results in a longer period for t bit-check requiring a higher value for the transmitter pre-burst t preburst . receiving mode if the bit check was successful for all bits specified by n bit-check , the receiver switches to receiving mode. ac- cording to figure 9, the internal data signal is switched to pin data in that case and the data clock is available after the start bit has been detected (figure 20). a connected c can be woken up by the negative edge at pin data or by the data clock at pin data_clk. the receiver stays in that condition until it is switched back to polling mode ex- plicitly.
t5761 T5760 / preliminary information rev. a2, 19-oct-00 11 (32) digital signal processing the data from the ask/ fsk demodulator (dem_out) is digitally processed in different ways and as a result con- verted into the output signal data. this processing depends on the selected baud-rate range (br_range). figure 14 illustrates how dem_out is synchronized by the extended clock cycle t xclk . this clock is also used for the bit-check counter. data can change its state only after t xclk has elapsed. the edge-to-edge time period t ee of the data signal as a result is always an integral multiple of t xclk . the minimum time period between two edges of the data signal is limited to t ee t data_min . this implies an effi- cient suppression of spikes at the data output. at the same time it limits the maximum frequency of edges at data. this eases the interrupt handling of a connected c. the maximum time period for data to stay low is lim- ited to t data_l_max . this function is employed to ensure a finite response time in programming or switching off the receiver via pin data. t data_l_max is thereby longer than the maximum time period indicated by the transmit- ter data stream. figure 16 gives an example where dem_out remains low after the receiver has switched to receiving mode. clock bit ? check counter data_out (data) t xclk dem_out t ee figure 14. synchronization of the demodulator output data_out (data) dem_out t ee t ee t data_min t ee t data_min t data_min figure 15. debouncing of the demodulator output bit check ic_active data_out (data) start ? up mode receiving mode t data_l_max t data_min bit ? check mode dem_out figure 16. steady l state limited data output pattern after transmission
T5760 t5761 / rev. a2, 19-oct-00 preliminary information 12 (32) after the end of a data transmission, the receiver remains active. depending of the bit noise_disable in the op- mode register, the output signal at pin data is high or random noise pulses appear at pin data (see chapter ? digital noise supression ? ). the edge-to-edge time pe- riod t ee of the majority of these noise pulses is equal or slightly higher than t data_min . switching the receiver back to sleep mode the receiver can be set back to polling mode via pin data or via pin polling/_on. when using pin data, this pin must be pulled to low for the period t1 by the connected c. figure 17 illustrates the timing of the off command (see also figure 32). the minimum value of t1 depends on br_range. the maxi- mum value for t1 is not limited but it is recommended not to exceed the specified value to prevent erasing the reset marker. note also that an internal reset for the opmode and the limit register will be generated if t1 exceeds the specified values. this item is explained in more detail in the chapter ? configuration of the receiver ? . setting the receiver to sleep mode via data is achieved by program- ming bit 1 to be ? 1 ? during the register configuration. only one sync pulse (t3) is issued. the duration of the off command is determined by the sum of t1, t2 and t10. after the off command the sleep time t sleep elapses. note that the capacitive load at pin data is limited (see chapter ? data interface ? ). data_out (data) serial bi ? directional data line x bit 1 ( ? 1 ? ) x t1 t2 t3 t4 t5 t7 (start bit) start ? up mode off ? command t sleep receiving mode t10 sleep mode t start ? up ic_active out1 ( c) figure 17. timing diagram of the off-command via pin data polling/_on data_out (data) serial bi ? directional data line receiving mode x sleep mode start ? up mode bit ? check mode receiving mode x bit check ok x x t on2 t on3 ic_active figure 18. timing diagram of the off-command via pin polling/_on
t5761 T5760 / preliminary information rev. a2, 19-oct-00 13 (32) polling/_on data_out (data) serial bi ? directional data line sleep mode receiving mode x x t on1 start ? up mode ic_active figure 19. activating the receiving mode via pin polling/_on figure 18 illustrates how to set the receiver back to poll- ing mode via pin polling/_on. the pin polling/_on must be held to low for the time period t on2 . after the positive edge on pin polling/_on and the delay t on3 , the polling mode is active and the sleep time t sleep elapses. this command is faster than using pin data at the cost of an additional connection to the c. figure 19 illustrates how to set the receiver to receiving mode via the pin polling/_on. the pin poll- ing/_on must be held to low. after the delay t on1 , the receiver changes from sleep mode to start ? up mode re- gardless the programmed values for t sleep and n bit ? check . as long as polling/_on is held to low, the values for t sleep and n bit ? check will be ignored, but not deleted (see also chapter ? digital noise suppression ? ). if the receiver is polled exclusively by a c, t sleep must be programmed to 31 (permanent sleep mode). in this case the receiver remains in sleep mode as long as poll- ing/_on is held to high. data clock the pin data_clk makes a data shift clock available to sample the data stream into a shift register. using this data clock, a c can easily synchronize the data stream. this clock can only be used for manchester and bi- phase coded signals. generation of the data clock: after a successful bit check, the receiver switches from polling mode to receiving mode and the data stream is available at pin data. in receiving mode, the data clock control logic (manchester/bi-phase demodulator) is ac- tive and examines the incoming data stream. this is done, like in the bit check, by subsequent time frame checks where the distance between two edges is continuously compared to a programmable time window. as illustrated in figure 20, only two distances between two edges in manchester and bi-phase coded signals are valid (t and 2t). the limits for t are the same as used for the bit check. they can be programmed in the limit-register (lim_min and lim_max, see tables 10 and 11). the limits for 2t are calculated as follows: lower limit of 2t: lim_min_2t = (lim_min + lim_max) ? (lim_max ? lim_min) / 2 upper limit of 2t: lim_max_2t= (lim_min + lim_max) + (lim_max ? lim_min) / 2 (if the result for ? lim_min_2t ? or ? lim_max_2t ? is not an integer value, it will be round up) the data clock is available, after the data clock control logic has detected the distance 2t (start bit) and is issued with the delay t delay after the edge on pin data (see fig- ure 20). if the data clock control logic detects a timing or logical error (manchester code violation), like illustrated in fig- ures 21 and 22, it stops the output of the data clock. the receiver remains in receiving mode and starts with the bit check. if the bit check was successful and the start bit has been detected, the data clock control logic starts again with the generation of the data clock (see figure 23). it is recommended to use the function of the data clock only in conjunction with the bit check 3, 6 or 9. if the bit check is set to 0 or the receiver is set to receiving mode via the pin polling/_on, the data clock is available if the data clock control logic has detected the distance 2t (start bit). note that for bi-phase-coded signals, the data clock is is- sued at the end of the bit.
T5760 t5761 / rev. a2, 19-oct-00 preliminary information 14 (32) dem_out data_out (data) data_clk ? 1 ? ? 1 ?? 1 ?? 1 ?? 1 ? ? 0 ?? 1 ?? 1 ?? 0 ?? 1 ?? 0 ? bit check ok preburst data t delay t p_data_clk t2t receiving mode, data clock control logic active bit ? check mode start bit figure 20. timing diagram of the data clock dem_out data_out (data) data_clk ? 1 ? ? 1 ?? 1 ?? 1 ?? 1 ? ? 0 ?? 1 ?? 1 ?? 0 ?? 1 ?? 0 ? timing error data ( t ee < t lim_min or t lim_max < t ee < t lim_min_2t or t ee > t lim_max_2t ) t ee receiving mode, bit check active receiving mode, data clock control logic active figure 21. data clock disappears because of a timing error dem_out data_out (data) data_clk ? 1 ? ? 1 ?? 1 ?? 0 ?? 1 ? ? 1 ?? ? ?? 0 ?? 0 ?? 1 ?? 0 ? logical error (manchester code violation) data receiving mode, bit check aktive receiving mode, data clock control logic active figure 22. data clock disappears because of a logical error
t5761 T5760 / preliminary information rev. a2, 19-oct-00 15 (32) dem_out data_out (data) data_clk ? 1 ? ? 1 ?? 1 ?? 1 ?? 1 ? ? 0 ?? 1 ?? 1 ?? 0 ?? 1 ?? 0 ? bit check ok data receiving mode, bit check active receiving mode, data clock control logic active start bit figure 23. output of the data clock after a successful bit check the delay of the data clock is calculated as follows: t delay = t delay1 + t delay2 t delay1 is the delay between the internal signals data_out and data_in. for the rising edge, t delay1 depends on the capacitive load c l at pin data and the external pull ? up resistor r pup . for the falling edge, t delay1 depends addi- tionally on the external voltage v x (see figures 24, 25 and 32). when the level of data_in is equal to the level of data_out, the data clock is issued after an additional delay t delay2 . note that the capacitive load at pin data is limited. if the maximum tolerated capacitive load at pin data is ex- ceeded, the data clock disappears (see chapter ? data interface ? ). v il = 0,35 * v s v ih = 0,65 * v s v x data_clk serial bi ? directional data line t delay1 t p_data_clk data_out data_in t delay2 t delay figure 24. timing characteristic of the data clock (rising edge on pin data) v il = 0,35 * vs v ih = 0,65 * vs v x data_clk serial bi ? directional data line t delay1 t p_data_clk data_out data_in t delay2 t delay figure 25. timing characteristic of the data clock (falling edge of the pin data)
T5760 t5761 / rev. a2, 19-oct-00 preliminary information 16 (32) digital noise suppression after a data transmission, digital noise appears on the data output (see figure 26). to prevent that digital noise keeps the connected c busy, it can be suppressed in two differ- ent ways. 1. automatic noise suppression: if the bit noise_disable (table 9) in the opmode register is set to 1 (default), the receiver changes to bit-check mode at the end of a valid data stream. the digital noise is suppressed and the level at pin data is high in that case. the receiver changes back to receiving mode, if the bit check was successful. this way to suppress the noise is recommended if the data stream is manchester or bi-phase coded and is active after power on. figure 28 illustrates the behavior of the data output at the end of a data stream. note that if the last period of the data stream is a high period (rising edge to falling edge), a pulse occurs on pin data. the length of the pulse depends on the selected baud-rate range. data_out (data) data_clk preburst data digital noise preburst data digital noise digital noise bit check ok bit ? check mode bit check ok receiving mode, bit check aktive receiving mode, bit check aktive receiving mode, data clock control logic active receiving mode, data clock control logic active figure 26. output of digital noise at the end of the data stream data_out (data) data_clk preburst data preburst data bit check ok bit check ok bit ? check mode bit ? check mode bit ? check mode receiving mode, data clock control logic active receiving mode, data clock control logic active figure 27. automatic noise suppression dem_out data_out (data) data_clk ? 1 ? ? 1 ?? 1 ? timing error t ee bit ? check mode receiving mode, data clock control logic active data stream digital noise t pulse (t ee < t lim_min or t lim_max < t ee < t lim_min_2t or t ee > t lim_max_2t ) figure 28. occurence of a pulse at the end of the data stream
t5761 T5760 / preliminary information rev. a2, 19-oct-00 17 (32) 2. controlled noise suppression by the c: serial bi ? directional data line (data_clk) preburst data digital noise preburst data digital noise bit check ok bit check ok receiving mode polling/_on off ? command receiving mode start ? up mode bit ? check mode sleep mode bit ? check mode figure 29. controlled noise suppression if the bit noise_disable (see table 9) in the opmode reg- ister is set to 0, digital noise appears at the end of a valid data stream. to suppress the noise, the pin poll- ing/_on must be set to low. the receiver remains in receiving mode. then, the off-command causes the change to the start-up mode. the programmed sleep time (see table 7) will not be executed because the level at pin polling/_on is low, but the bit check is active in that case. the off-command activates the bit check also if the pin polling/_on is held to low. the receiver changes back to receiving mode if the bit check was suc- cessful. to activate the polling mode at the end of the data transmission, the pin polling/_on must be set to high. this way to suppress the noise is recommended if the data stream is not manchester or bi-phase coded. configuration of the receiver the T5760/t5761 receiver is configured via two 12-bit ram registers called opmode and limit. the regis- ters can be programmed by means of the bidirectional data port. if the register contents have changed due to a voltage drop, this condition is indicated by a certain out- put pattern called reset marker (rm). the receiver must be reprogrammed in that case. after a power-on reset (por), the registers are set to default mode. if the receiver is operated in default mode, there is no need to program the registers. table 3 shows the structure of the registers. according to table 2 bit 1 defines if the receiver is set back to polling mode via the off command (see chapter ? receiving mode ? ) or if it is programmed. bit 2 repre- sents the register address. it selects the appropriate register to be programmed. to get a high programming reliability, bit15 (stop bit), at the end of the programming operation, must be set to 0. table 1 effect of bit 1 and bit 2 on programming the registers bit 1 bit 2 action 1 x the receiver is set back to polling mode (off command) 0 1 the opmode register is pro- grammed 0 0 the limit register is programmed table 2 effect of bit 15 on programming the register bit 15 action 0 the values will be written into the register (opmode or limit) 1 the values will not be written into the register
T5760 t5761 / rev. a2, 19-oct-00 preliminary information 18 (32) table 3 effect of the configuration words within the registers bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 9 bit 10 bit 11 bit 12 bit 13 bit 14 bit 15 off ? command 1 opmode register br_range n bit ? check modu- lation sleep x sleep noise suppres- sion 0 1 baud1 baud0 bitchk 1 bitchk 0 ask/_ fsk sleep4 sleep3 sleep2 sleep1 sleep0 x sleep std noise_d isable 0 default values of bit 3...14 0 0 0 1 0 0 0 1 1 0 0 1 limit register lim_min lim_max 0 0 lim_ min5 lim_ min4 lim_ min3 lim_ min2 lim_ min1 lim_ min0 lim_ max5 lim_ max4 lim_ max3 lim_ max2 lim_ max1 lim_ max0 0 default values of bit 3...14 0 1 0 1 0 1 1 0 1 0 0 1 the following tables illustrate the effect of the individual configuration words. the default configuration is highlighted for each word. br_range sets the appropriate baud ? rate range and simultaneously defines xlim. xlim is used to define the bit ? check limits t lim_min and t lim_max as shown in table 10 and table 11. table 4 effect of the configuration word br_range br_range baud-rate range / extension factor for bit-check limits (xlim) baud1 baud0 0 0 br_range0 (application usa / europe: br_range0 = 1.0 kbaud to 1.8 kbaud) (de- fault) xlim = 8 (default) 0 1 br_range1 (application usa / europe: br_range1 = 1.8 kbaud to 3.2 kbaud) xlim = 4 1 0 br_range2 (application usa / europe: br_range2 = 3.2 kbaud to 5.6 kbaud) xlim = 2 1 1 br_range3 (application usa / europe: br_range3 = 5.6 kbaud to 10 kbaud) xlim = 1 table 5 effect of the configuration word n bit-check n bit-check number of bits to be checked bitchk1 bitchk0 0 0 0 0 1 3 (default) 1 0 6 1 1 9
t5761 T5760 / preliminary information rev. a2, 19-oct-00 19 (32) table 6 effect of the configuration bit modulation modulation selected modulation ask/_fsk 0 fsk 1 ask table 7 effect of the configuration word sleep sleep start value for sleep counter (t sleep = sleep xsleep 1024 t clk ) sleep4 sleep3 sleep2 sleep1 sleep0 0 0 0 0 0 0 (receiver is continuously polling until a valid signal occurs) 0 0 0 0 1 1 (t sleep 2.1 ms for xsleep =1 and f rf = 868.3 ms, 1.96 ms for f rf = 915 mhz) 0 0 0 1 0 2 0 0 0 1 1 3 . . . . . . . . . . . . . . . . . . 0 0 1 1 0 6 (t sleep = 12.695 ms for f rf = 868.3 mhz, 11.76 ms for f rf = 915 mhz) . . . . . . . . . . . . . . . . . . 1 1 1 0 1 29 1 1 1 1 0 30 1 1 1 1 1 31 (permanent sleep mode) table 8 effect of the configuration bit xsleep xsleep extension factor for sleep time (t sleep = sleep xsleep 1024 t clk ) xsleep std sleep clk 0 1 (default) 1 8 table 9 effect of the configuration bit noise suppression noise suppression suppression of the digital noise at pin data noise_disable 0 noise suppression is inactive 1 noise suppression is active (default)
T5760 t5761 / rev. a2, 19-oct-00 preliminary information 20 (32) table 10 effect of the configuration word lim_min lim_min *) (lim_min < 10 is not applicable) lower limit value for bit check lim_min5 lim_min4 lim_min3 lim_min2 lim_min1 lim_min0 (t lim_min = lim_min xlim t clk ) 0 0 1 0 1 0 10 0 0 1 0 1 1 11 0 0 1 1 0 0 12 . . . . . . . . . . . . 0 1 0 1 0 1 21 (default) (t lim_min = 347 s for f rf = 868.3 mhz and br_range0 t lim_min = 329 s for f rf = 915 mhz and br_range0) . . . . . . . . . . . . 1 1 1 1 0 1 61 1 1 1 1 1 0 62 1 1 1 1 1 1 63 *) lim_min is also be used to determine the margins of the data clock control logic (see chapter ? data clock ? ) table 11 effect of the configuration word lim_max lim_max *) ( lim_max < 12 is not applicable) upper limit value for bit check lim_max5 lim_max4 lim_max3 lim_max2 lim_max1 lim_max0 (t lim_max = (lim_max ? 1) xlim t clk ) 0 0 1 1 0 0 12 0 0 1 1 0 1 13 0 0 1 1 1 0 14 . . . . . . . . . . . . 1 0 1 0 0 1 41 (default) (t lim_max = 677 s for f rf = 868.3 mhz and br_range0, t lim_max = 642 s for f rf = 915 mhz and br_range0) . . . . . . . . . . . . 1 1 1 1 0 1 61 1 1 1 1 1 0 62 1 1 1 1 1 1 63 *) lim_max is also be used to determine the margins of the data clock control logic (see chapter ? data clock ? ) conservation of the register information the T5760/t5761 implies an integrated power-on reset and brown-out detection circuitry to provide a mecha- nism to preserve the ram register information. according to figure 30 , a power ? on reset (por) is gener- ated if the supply voltage v s drops below the threshold voltage v threset . the default parameters are pro- grammed into the configuration registers in that condition. once v s exceeds v threset the por is canceled after the minimum reset period t rst . a por is also gener- ated when the supply voltage of the receiver is turned on. to indicate that condition, the receiver displays a reset marker (rm) at pin data after a reset. the rm is repre- sented by the fixed frequency f rm at a 50% duty-cycle. rm can be canceled via a low pulse t1 at pin data. the rm implies the following characteristics: f rm is lower than the lowest feasible frequency of a data signal. by this means, rm cannot be misinter- preted by the connected c. if the receiver is set back to polling mode via pin data, rm cannot be canceled by accident if t1 is ap- plied according to the proposal in the section ? programming the configuration registers ? . by means of that mechanism the receiver cannot lose its register information without communicating that condi- tion via the reset marker rm.
t5761 T5760 / preliminary information rev. a2, 19-oct-00 21 (32) v s por data_out (data) 1 / f rm t rst v threset x figure 30. generation of the power-on reset programming the configuration register out1 ( data_out (data) serial bi ? directional data line x bit 1 ( ? 0 ? ) bit 2 ( ? 1 ? ) bit 14 ( ? 0 ? ) bit 15 ( ? 0 ? ) x t1 t2 t3 t4 t5 t6 t8 t7 programming frame (start bit) (register ? select) (poll8) (stop bit) receiving mode start ? up mode t9 ic_active t sleep t start ? up sleep mode figure 31. timing of the register programming data_in data_out input ? interface data 0 ... 20 v 0 v / 5 v v x = 5 v to 20 v r pup c l v s = 4.5 v to 5.5 v i/o serial bi ? directional data line T5760/ t5761 c out1 c i d figure 32. data interface the configuration registers are programmed serially via the bi-directional data line according to figure 31 and figure 32.
T5760 t5761 / rev. a2, 19-oct-00 preliminary information 22 (32) to start programming, the serial data line data is pulled to low for the time period t1 by the c. when data has been released, the receiver becomes the master device. when the programming delay period t2 has elapsed, it emits 15 subsequent synchronization pulses with the pulse length t3. after each of these pulses, a programming window occurs. the delay until the program window starts is determined by t4, the duration is defined by t5. within the programming window, the individual bits are set. if the c pulls down pin data for the time period t7 during t5, the according bit is set to ? 0 ? . if no program- ming pulse t7 is issued, this bit is set to ? 1 ? . all 15 bits are subsequently programmed this way. the time frame to program a bit is defined by t6. bit 15 is followed by the equivalent time window t9. dur- ing this window, the equivalence acknowledge pulse t8 (e_ack) occurs if the just programmed mode word is equivalent to the mode word that was already stored in that register. e_ack should be used to verify that the mode word was correctly transferred to the register. the register must be programmed twice in that case. programming of a register is possible both in sleep ? and in active ? mode of the receiver. during programming, the lna, lo, lowpass filter if- amplifier and the fsk/ask manchester demodulator are disabled. the programming start pulse t1 initiates the program- ming of the configuration registers. if bit 1 is set to ? 1 ? , it represents the off ? command to set the receiver back to polling mode at the same time. for the length of the pro- gramming start pulse t1, the following convention should be considered: t1(min) < t1 < 5632 t clk : t1(min) is the minimum specified value for the relevant br_range programming respectively off-command is initiated if the receiver is not in reset mode.if the receiver is in reset mode, programming respectively off-command is not in- itiated and the reset marker rm is still present at pin data. this period is generally used to switch the receiver to pol- ling mode or to start the programming of a register. in reset condition, rm is not cancelled by accident. t1 > 7936 t clk programming respectively off ? command is initiated in any case. the registers opmode and limit are set to the default values. rm is cancelled if present. this period is used if the connected c detected rm.if the receiver operates in default mode, this time period for t1 can generally be used. note that the capacitive load at pin data is limited. data interface the data interface (see figure 32) is designed for automo- tive requirements. it can be connected via the pull ? up resistor r pup up to 20v and is short ? circuit ? protected. the applicable pull-up resistor r pup depends on the load capacity c l at pin data and the selected br_range (see table 12). more detailed information about the calcula- tion of the maximum load capacity at pin data is given in the ? application hints t5743n ? . table 12 applicable r pup br_range applicable r pup c l 1nf b0 1.6 k ? to 47 k ? b1 1.6 k ? to 22 k ? b2 1.6 k ? to 12 k ? b3 1.6 k ? to 5.6 k ? c l 100pf b0 1.6 k ? to 470 k ? b1 1.6 k ? to 220 k ? b2 1.6 k ? to 120 k ? b3 1.6 k ? to 56 k ?
t5761 T5760 / preliminary information rev. a2, 19-oct-00 23 (32) c7 4.7u 10% vs r3 >= 1.6k data polling/_on r2 56k to 150k sens 1 ic_active 2 cdem 3 av c c 4 test1 5 agnd 6 n.c. 7 lnaref 8 lna_in 9 lnagnd 10 test2 11 test3 12 n.c. 13 xtal 14 dvcc 15 test4 16 data_clk 17 dgnd 18 polling/_on 19 data 20 c14 33n 5% gnd c13 10n 10% q1 6.77617 mhz c11 12p 2% data_clk c16 150p 10% toko ll2012 c17 2.2p 5% rf_in np0 np0 np0 sensitivity reduction ic_active c12 10n 10% T5760/ t5761 v x = 5 v to 20 v f5n6j 5.6 nh, 5% figure 33. application circuit: f rf = 868.3 mhz without saw filter c7 4.7u 10% vs r3 >= 1.6k data polling/_on r2 56k to 150k sens 1 ic_active 2 cdem 3 av c c 4 test1 5 agnd 6 n.c. 7 lnaref 8 lna_in 9 lnagnd 10 test2 11 test3 12 n.c. 13 xtal 14 dvcc 15 test4 16 data_clk 17 dgnd 18 polling/_on 19 data 20 c14 33n 5% gnd c13 10n 10% q1 c11 12p 2% data_clk np0 sensitivity reduction ic_active c12 10n 10% T5760/ t5761 v x = 5 v to 20 v c16 18p 5% c17 5.6p 5% in 1 in_gnd 2 case_gnd 3 case_gnd 4 out 5 out_gnd 6 case_gnd 7 case_gnd 8 epcos b3570 rf_in c2 3.3p 5% np0 np0 np0 toko ll2012 toko ll2012 f15nj 15n, 5% 6.77617 mhz f5n6j 5.6 nh, 5% figure 34. application circuit: f rf = 868.3 mhz with saw filter
T5760 t5761 / rev. a2, 19-oct-00 preliminary information 24 (32) absolute maximum ratings parameter symbol min. max. unit supply voltage v s 6 v power dissipation p tot 1000 mw junction temperature t j 150 c storage temperature t stg ? 55 +125 c ambient temperature t amb ? 40 +105 c maximum input level, input matched to 50 p in_max 10 dbm thermal resistance parameter symbol value unit junction ambient r thja 100 k/w electrical characteristics all parameters refer to gnd, t amb = ? 40 c to +105 c, v s = 4.5 v to 5.5 v, f 0 = 868.3 mhz and f 0 = 915 mhz, un- less otherwise specified. (for typical values: v s = 5 v, t amb = 25 c) parameter test conditions symbol f rf = 868.3 mhz 6.77617 mhz osc. f rf = 915 mhz 7.14063 mhz osc. variable oscillator unit min. typ. max. min. typ. max. min. typ. max. basic clock cycle of the digital circuitry basic clock cycle t clk 2.0662 2.0662 1.9607 1.9607 1/f xto /14 1/f xto /14 s extended basic clock cycle br_range0 br_range1 br_range2 br_range3 t xclk 16.53 8.26 4.13 2.07 16.53 8.26 4.13 2.07 15.69 7.84 3.92 1.96 15.69 7.84 3.92 1.96 8 t clk 4 t clk 2 t clk 1 t clk 8 t clk 4 t clk 2 t clk 1 t clk s s s s polling mode sleep time see figures 11, 20 and 33 sleep and xsleep are defined in the opmode register t sleep sleep x sleep 1024 2.0662 sleep x sleep 1024 2.0662 sleep x sleep 1024 1.9607 sleep x sleep 1024 1.9607 sleep x sleep 1024 t clk sleep x sleep 1024 t clk ms start-up time see figures 11 and 12 br_range0 br_range1 br_range2 br_range3 t startup 1852 1059 1059 662 1852 1059 1059 662 1758 1049 1049 628 1758 1049 1049 628 896.5 512.5 512.5 320.5 t clk 896.5 512.5 512.5 320.5 t clk s s s s s time for bit check see figure 11 average bit-check time while polling, no rf applied, see figures 15 and 16 br_range0 br_range1 br_range2 br_range3 t bit-check 0.45 0.24 0.14 0.08 0.45 0.24 0.14 0.08 ms ms ms ms bit-check time for a valid input signal f sig , see figure 12 n bit-check = 0 n bit-check = 3 n bit-check = 6 n bit-check = 9 t bit-check 3/f sig 6/f sig 9/f sig 3.5/f sig 6.5/f sig 9.5/f sig 3/f sig 6/f sig 9/f sig 3.5/f sig 6.5/f sig 9.5/f sig 1 t xclk 3/f sig 6/f sig 9/f sig 1 t clk 3.5/f sig 6.5/f sig 9.5/f sig ms ms ms ms
t5761 T5760 / preliminary information rev. a2, 19-oct-00 25 (32) electrical characteristics (continued) all parameters refer to gnd, t amb = ? 40 c to +105 c, v s = 4.5 v to 5.5 v, f 0 = 868.3 mhz and f 0 = 915 mhz, un- less otherwise specified. (for typical values: v s = 5 v, t amb = 25 c) parameter test conditions symbol f rf = 868.3 mhz 6.77617 mhz osc. f rf = 915 mhz 7.14063 mhz osc. variable oscillator unit min. typ. max. min. typ. max. min. typ. max. receiving mode intermediate frequency f if 1.000 1.054 f xto 128 / 867.3 mhz baud-rate range br_range0 br_range1 br_range2 br_range3 br_range 1.0 1.8 3.2 5.6 1.8 3.2 5.6 10.0 1.054 1.89 3.38 5.9 1.89 3.38 5.9 10.5 br_range0 2 s / t clk br_range1 2 s / t clk br_range2 2 s / t clk br_range3 2 s / t clk kbaud kbaud kbaud kbaud minimum time period between edges at pin data see figures 18 and 19 (with the ex- ception of pa- rameter t pulse ) br_range = br_range0 br_range1 br_range2 br_range3 t data_min 165.3 82.6 41.3 20.7 165.3 82.6 41.3 20.7 156.8 78.4 39.2 19.6 156.8 78.4 39.2 19.6 10 t xclk 10 t xclk 10 t xclk 10 t xclk 10 t xclk 10 t xclk 10 t xclk 10 t xclk s s s s maximum low period at pin data see figure 16 br_range = br_range0 br_range1 br_range2 br_range3 t data_l_m ax 2149 1074 537 269 2149 1074 537 269 2139 1020 510 255 2139 1020 510 255 130 t xclk 130 t xclk 130 t xclk 130 t xclk 130 t xclk 130 t xclk 130 t xclk 130 t xclk s s s s delay to acti- vate the start-up mode see figure 22 ton1 19.6 21.7 18.6 20.6 9.5 t clk 10.5 t clk s off ? com- mand at pin poll- ing/_on see figure 21 ton2 16.5 15.6 8 t clk s delay to acti- vate the sleep mode see figure 21 ton3 17.6 19.6 16.6 18.6 8.5 t clk 9.5 t clk s pulse on pin data at the end of a data stream see figure 30 br_range = br_range0 br_range1 br_range2 br_range3 t pulse 16.5 8.3 4.1 2.1 16.5 8.3 4.1 2.1 15.69 7.84 3.92 1.96 15.69 7.84 3.92 1.96 8 t clk 4 t clk 2 t clk 1 t clk 8 t clk 4 t clk 2 t clk 1 t clk s s s s
T5760 t5761 / rev. a2, 19-oct-00 preliminary information 26 (32) electrical characteristics (continued) all parameters refer to gnd, t amb = ? 40 c to +105 c, v s = 4.5 v to 5.5 v, f 0 = 868.3 mhz and f 0 = 915 mhz, un- less otherwise specified. (for typical values: v s = 5 v, t amb = 25 c) parameter test conditions symbol f rf = 868.3 mhz 6.77617 mhz osc. f rf = 915 mhz 7.14063 mhz osc. variable oscillator unit min. typ. max. min. typ. max. min. typ. max. configuration of the receiver (see figures 17 and 33) freque ncy of the re- set marker frequency is stable within 50 ms after por f rm 118.2 118.2 124.5 124.5 1 4096 t clk 1 4096 t clk hz programming start pulse br_range = br_range0 br_range1 br_range2 br_range3 after por t1 3355 2273 1731 1461 16397 11637 11637 11637 11637 3184 2168 1643 1386 15560 11043 11043 11043 11043 1624 t clk 1100 t clk 838 t clk 707 t clk 7936 t clk 5632 t clk 5632 t clk 5632 t clk 5632 t clk s s s s s programming delay period t2 795 797 754 756 384.5 t clk 385.5 t clk s synchroni ? zation pulse t3 264 264 251 251 128 t clk 128 t clk s delay until of the program window starts t4 131 131 125 125 63.5 t clk 63.5 t clk s programming window t5 529 529 502 502 256 t clk 256 t clk s time frame of a bit t6 1058 1058 1004 1004 512 t clk 512 t clk s programming pulse t7 132 529 125 502 64 t clk 256 t clk s equivalent acknowledge pulse: e_ack t8 264 264 251 251 128 t clk 128 t clk s equivalent time window t9 533 533 506 506 258 t clk 258 t clk s off-bit pro- gramming window t10 929 929 881 881 449.5 t clk 449.5 t clk s data clock (see figures 27 and 28) minimum delay time be- tween edge @ data and data_clk br_range = br_range0 br_range1 br_range2 br_range3 t delay2 0 0 0 0 16.5 8.3 4.1 2.1 0 0 0 0 16.7 7.8 3.9 1.96 0 0 0 0 1 t xclk 1 t xclk 1 t xclk 1 t xclk s s s s pulswidth of negative pulse @ pin data_clk br_range = br_range0 br_range1 br_range2 br_range3 t p_data_ clk 66.1 33.0 16.5 8.3 66.1 33.0 16.5 8.3 63 31 15.7 7.8 63 31 15.7 7.8 4 t xclk 4 t xclk 4 t xclk 4 t xclk 4 t xclk 4 t xclk 4 t xclk 4 t xclk s s s s
t5761 T5760 / preliminary information rev. a2, 19-oct-00 27 (32) electrical characteristics (continued) all parameters refer to gnd, t amb = ? 40 c to +105 c, v s = 4.5 v to 5.5 v, f 0 = 868.3 mhz and f 0 = 915 mhz, un- less otherwise specified. (for typical values: v s = 5 v, t amb = 25 c) parameters test conditions / pins symbol min. typ. max. unit current consumption sleep mode (xto and polling logic active) is off 170 276 a ic active (start-up-, bit check-, receiving mode) pin data = h fsk ask is on 7.8 7.4 9.9 9.6 ma ma lna, mixer, polyphase lowpass and if amplifier (input matched according to figure 33 referred to rf in ) third-order intercept point lna/ mixer/ if amplifier iip3 ? 16 dbm lo spurious emission required according to i ? ets 300220 is lorf ? 70 ? 57 dbm system noise figure with power matching |s11| < ? 10 db nf 5 db lna_in input impedance @ 868.3 mhz @ 915 mhz zi lna_in 200 || 3.2 200 || 3.2 ? || pf ? || pf 1 db compression point ip 1db ? 25 dbm image rejection within the complete image band 30 20 db maximum input level ber 10 ? 3 , fsk mode ask mode p in_max ? 10 ? 10 dbm dbm local oscillator operating frequency range vco T5760 t5761 f vco f vco 866 900 871 929 mhz mhz phase noise local oscillator f osc = 867.3 mhz @ 10 mhz l (fm) ? 140 ? 130 dbc/hz spurious of the vco @ f xto ? 55 ? 45 dbc xto pulling xto pulling, appropriate load capacitance must be connected to xtal, crystal c m = 7 ff f xtal = 6.77617 mhz (eu) f xtal = 7.14063 mhz (us) f xto ? 30 ppm f xtal +30 ppm mhz series resonance resistor of the crystal parameter of the supplied crystal r s 120 static capacitance at pin xtal to gnd parameter of the supplied crystal and board parasitics c 0 6.5 pf
T5760 t5761 / rev. a2, 19-oct-00 preliminary information 28 (32) electrical characteristics (continued) all parameters refer to gnd, t amb = ? 40 c to +105 c, v s = 4.5 v to 5.5 v, f 0 = 868.3 mhz and f 0 = 915 mhz, un- less otherwise specified. (for typical values: v s = 5 v, t amb = 25 c) parameters test conditions / pins symbol min. typ. max. unit analog signal processing (input matched according to figure 33 referred to rf in) input sensitivity ask ask (level of carrier) ber 10 ? 3, 100% mod f in = 868.3 mhz / 915 mhz v s = 5 v, t amb = 25 c f if = 950 khz/ 1 mhz br_range0 p ref_ask ? 110 ? 112 ? 114 dbm br_range1 ? 108.5 ? 100.5 ? 112.5 dbm br_range2 ? 108 ? 110 ? 108 dbm br_range3 ? 106 ? 108 ? 110 dbm sensitivity variation ask for the full operating range compared to t amb = 25 c, v s = 5 v f in = 868.3 mhz / 915 mhz f if = 950 khz/ 1 mhz p ask = p ref_ask + p ref p ref +2.5 ? 1.0 db sensitivity variation ask for full operating range includ- ing if filter compared to t amb = 25 c, v s = 5 v, f in = 868.3 mhz / 915 mhz f if = 950 khz/ 1 mhz f if ? 210 khz to + 210 khz f if ? 270 khz to + 270 khz p ask = p ref_ask + p ref , p ref +5.5 +7.5 ? 1.5 ? 1.5 db db input sensitivity fsk ber 10 ? 3 f in = 868.3 mhz / 915 mhz v s = 5 v, t amb = 25 c f if = 950 khz/ 1 mhz br_range0 df = +/ ? 16 khz to 28 khz df = +/ ? 10 khz to +/ ? 100 khz p ref_fsk ? 103 ? 101 ? 106 ? 107.5 ? 107.5 dbm dbm br_range1 df = +/ ? 16 khz to 28 khz df = +/ ? 10 khz to +/ ? 100 khz p ref_fsk ? 101 ? 99 ? 104 ? 105.5 ? 105.5 dbm dbm br_range2 df = +/ ? 18 khz to 31 khz df = +/ ? 13 khz to +/ ? 100 khz p ref_fsk ? 99.5 ? 97.5 ? 102.5 ? 104 dbm dbm br_range3 df = +/ ? 25 khz to 44 khz df = +/ ? 20 khz to +/ ? 100 khz p ref_fsk ? 97.5 ? 95.5 ? 100.5 ? 102 dbm dbm sensitivity variation fsk for the full operating range compared to t amb = 25 c, v s = 5 v f in = 868.3 mhz / 915 mhz f if = 950 khz/ 1 mhz p fsk = p ref_fsk + p ref p ref +3 ? 1.5 db sensitivity variation fsk for the full operating range in- cluding if filter compared to t amb = 25 c, v s = 5 v f in = 868.3 mhz / 915 mhz f if = 950 khz/ 1 mhz f if ? 150 khz to + 150 khz f if ? 200 khz to + 200 khz f if ? 260 khz to + 260 khz p fsk = p ref_fsk + p ref p ref +6 +8 +11 ? 2 ? 2 ? 2 db db db
t5761 T5760 / preliminary information rev. a2, 19-oct-00 29 (32) electrical characteristics (continued) all parameters refer to gnd, t amb = ? 40 c to +105 c, v s = 4.5 v to 5.5 v, f 0 = 868.3 mhz and f 0 = 915 mhz, un- less otherwise specified. (for typical values: v s = 5 v, t amb = 25 c) parameters test conditions / pins symbol min. typ. max. unit s/n ratio to suppress inband noise signals. noise signals may have any modulation scheme ask mode fsk mode snr ask snr fsk 10 2 12 3 db db dynamic range rssi ampl. dr rssi 60 db lower cut-off frequency of the data filter cdem = 33 nf f cu_df 1 2 30k cdem f cu_df 0.11 0.16 0.20 khz recommended cdem for best performance br_range0 (default) br_range1 br_range2 br_range3 cdem 39 22 12 8.2 nf nf nf nf edge-to-edge time period of the input data signal for full sensitivity br_range0 (default) br_range1 br_range2 br_range3 t ee_sig 270 156 89 50 1000 560 320 180 s s s s upper cut-off frequency data filter upper cut-off frequency pro- grammable in 4 ranges via a se- rial mode word br_range0 (default) br_range1 br_range2 br_range3 f u 2.8 4.8 8.0 15.0 3.4 6.0 10.0 19.0 4.0 7.2 12.0 23.0 khz khz khz khz reduced sensitivity r sense connected from pin sens to v s , input matched according to figure 33, f in = 868.3 mhz/ 915 mhz dbm (peak level) r sense = 56 k p ref_red ? 63 ? 68 ? 73 dbm r sense = 100 k p ref_red ? 72 ? 77 ? 82 dbm reduced sensitivity variation over full operating range r sense = 56 k r sense = 100 k p red = p ref_red + p red p red 5 5 0 0 0 0 db db reduced sensitivity variation for different values of r sense values relative to r sense = 56 k r sense = 56 k r sense = 68 k r sense = 82 k r sense = 100 k r sense = 120 k r sense = 150 k p red = p ref_red + p red p red p red p red p red p red p red 0 ? 3.5 ? 6.0 ? 9.0 ? 11.0 ? 13.5 db db db db db db threshold voltage for reset v threset 1.95 2.8 3.75 v
T5760 t5761 / rev. a2, 19-oct-00 preliminary information 30 (32) electrical characteristics (continued) all parameters refer to gnd, t amb = ? 40 c to +105 c, v s = 4.5 v to 5.5 v, f 0 = 868.3 mhz and f 0 = 915 mhz, un- less otherwise specified. (for typical values: v s = 5 v, t amb = 25 c) parameters test conditions / pins symbol min. typ. max. unit digital ports data output ? saturation voltage low ? max voltage @ pin data ? quiescent current ? short ? circuit current ? ambient temp. in case of permanent short ? circuit data input ? input voltage low ? input voltage high i ol 12 ma i ol = 2 ma v oh = 20 v v ol = 0.8 to 20 v v oh = 0v to 20 v v ol v ol v oh i qu i ol_lim t amb_sc v il v ich 13 0.65 v s 0.35 0.08 30 0.8 0.3 20 20 45 85 0.35 v s v v v a ma c v v data_clk output ? saturation voltage low ? saturation voltage high idata_clk = 1ma idata_clk = ? 1ma v ol v oh v s ? 0.4 v 0.1 v s ? 0.15 v 0.4 v v ic_active output ? saturation voltage low ? saturation voltage high iic_active = 1ma iic_active = ? 1ma v ol v oh v s ? 0.4 v 0.1 v s ? 0.15 v 0.4 v v polling/_on input ? low level input voltage ? high level input voltage receiving mode polling mode v il v ih 0.8 v s 0.2 v s v v mode input ? low level input voltage ? high level input voltage division factor = 10 division factor = 14 v il v ih 0.8 v s 0.2 v s v v test input ? low level input voltage test input must always be set to low v il 0.2 v s v
t5761 T5760 / preliminary information rev. a2, 19-oct-00 31 (32) package information 13038 technical drawings according to din specifications package so20 dimensions in mm 9.15 8.65 11.43 12.95 12.70 2.35 0.25 0.10 0.4 1.27 7.5 7.3 0.25 10.50 10.20 20 11 110
T5760 t5761 / rev. a2, 19-oct-00 preliminary information 32 (32) ozone depleting substances policy statement it is the policy of atmel germany gmbh to 1. meet all present and future national and international statutory requirements. 2. regularly and continuously improve the performance of our products, processes, distribution and operating systems with respect to their impact on the health and safety of our employees and the public, as well as their impact on the environment. it is particular concern to control or eliminate releases of those substances into the atmosphere which are known as ozone depleting substances (odss). the montreal protocol ( 1987) and its london amendments ( 1990) intend to severely restrict the use of odss and forbid their use within the next ten years. various national and international initiatives are pressing for an earlier ban on these substances. atmel germany gmbh has been able to use its policy of continuous improvements to eliminate the use of odss listed in the following documents. 1. annex a, b and list of transitional substances of the montreal protocol and the london amendments respectively 2. class i and ii ozone depleting substances in the clean air act amendments of 1990 by the environmental protection agency (epa) in the usa 3. council decision 88/540/eec and 91/690/eec annex a, b and c (transitional substances) respectively. atmel germany gmbh can certify that our semiconductors are not manufactured with ozone depleting substances and do not contain such substances. 12. we reserve the right to make changes to improve technical design and may do so without further notice . parameters can vary in different applications. all operating parameters must be validated for each customer application by the customer. should the buyer use atmel wireless & microcontrollers products for any unintended or unauthorized application, the buyer shall indemnify atmel wireless & microcontrollers against all claims, costs, damages, and expenses, arising out of, directly or indirectly, any claim of personal damage, injury or death associated with such unintended or unauthorized use. atmel germany gmbh, p.o.b. 3535, d-74025 heilbronn, germany telephone: 49 (0)7131 67 2594, fax number: 49 (0)7131 67 2423

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